Random access memory is an essential resource required by computational hardware. Since the processor speed has reached the GHz clock frequency, memory throughput can be a bottleneck to achieve high performance. DRAM can provide a reasonable solution for such data storage. The typical computational system consists of multiple hardware modules that perform different operations on data. These modules attempt to access data at the same time. This leads to a requirement for a memory controller that arbitrates between requests queried by different modules and exploits maximum throughput. The memory controller interfaces with DRAM and other subsystems. It then handles data in and out of memory. Access latency or access speed depends solely on the memory controller implementation. The work focuses on the relative study of two memory controllers, namely SDRAM controller and DDR SDRAM. The study includes analysis of the area, power and timing of both. The Synopsys Design Compiler tool is used to obtain the necessary results. Index Terms: SDRAM, DDR, ASIC, latency.I. INTRODUCTIONAny computational hardware or commonly computer system requires minimal storage space. The storage requirement can be satisfied by two different classes of memories, namely static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a flip-flop is used to hold information. A single-bit SRAM cell is made up of 6 transistors and stores information as a logic layer in a cross-connection of transistors. The advantages of SRAM are the absence of refresh mechanism, low power consumption and the absence of address multiplexing. Therefore making it suitable for higher levels of the memory pyramid where memory needs to be fast, such as in notes. SRAM has the disadvantage of low memory density and is expensive. When there is......half of the paper......ecks and a maximum on sys_dly_200us indicates the end of the clock stabilization delay. The initialization sequence begins immediately after clock/power stabilization concludes and then INIT_FSM will change its state from i_IDLE to i_NOP. The initialization FSM will transition from the i_NOP state to the i_PRE state in the next clock cycle. In the i_PRE state, the main control module generates the PRECHARGE command and this command is applied to all banks of the device. After the PRECHARGE command, INIT_FSM will transition to the next state. The next state in the FSM initialization design is two AUTO REFRESH commands. These commands will refresh the DRAM memory. After the two update cycles, the initialization FSM will transition to the i_MRS state. In this state, the LOAD MODE REGISTER command is generated to configure the SDRAM to a specific operating mode.